In the field of electronics various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design. Once the PLD has been programmed within a working system, however, it is also important to be able to debug the PLD in this real-world environment.
And although a simulation may be used to debug many aspects of a PLD, it is nearly impossible to generate a simulation that will accurately exercise all of the features of the PLD on an actual circuit board operating in a complex system. For example, a simulation may not be able to provide timing characteristics that are similar to those that will actually be experienced by the PLD in a running system; e.g., simulation timing signals may be closer or farther apart than what a PLD will actually experience in a real system.
In addition to the difficulties in generating a comprehensive simulation, circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a PLD that are only evident when the PLD is operating within a working system. Still further, it can be difficult to generate sufficiently varied test vectors to stress the PLD design to the point where most bugs are likely to be observed. For example, a PLD malfunction can result when the PLD is presented with stimuli that the designer did not expect, and therefore did not take into account during the design and simulation of the PLD. Such malfunctions are difficult to anticipate and must be debugged in the context of the complete system. Thus, simulation of an electronic design is useful, but usually cannot debug a PLD completely.
One approach to debugging a hardware device within a working system is to use a separate piece of hardware equipment called a logic analyzer to analyze signals present on the pins of a hardware device. Typically, a number of probe wires are connected manually from the logic analyzer to pins of interest on the hardware device in order to monitor signals on those pins. The logic analyzer captures and stores these signals for later viewing and debugging.
As an external logic analyzer may not always be optimal, embedding a logic analyzer within the hardware device is another technique used. For example, U.S. Pat. No. 6,182,247 entitled “Embedded Logic Analyzer For A Programmable Logic Device” discloses such a technique, and U.S. Pat. Nos. 6,286,114 and 6,247,147 disclose enhancements. In addition, viewing internal nodes in a device may be performed as disclosed in U.S. patent application Ser. No. 09/802,480 now U.S. Pat. No. 6,754,862. These techniques may fully recompile the electronic design before debugging can be performed. Embedding a logic analyzer into a design is also a technique used in the product “ChipScope ILA” available from Xilinx Inc., of San Jose, Calif. The product “ChipScope Pro” also available from Xilinx uses logic cores built directly into a PLD to allow a user to access internal signals and nodes for debugging.
Once an electronic design for a hardware device such as a PLD has been compiled, though, it may not be desirable to fully recompile the design in order to facilitate a debugging technique. For example, once a design has been compiled and programmed into a hardware device, the hardware may not function as intended even though a simulation of the design functioned correctly. If an internal signal needs to be debugged, existing techniques require the user to change the design to route the signal to an I/O pin of the hardware device (or require the user to program the signal into an internal logic analyzer), and then execute a full recompile. Or, due to hardware constraints, an internal signal may need to be routed from a current output pin to a different output pin to enable debugging; again, the design is changed and a full recompile is performed.
The recompilation may often re-place and re-route the design to fit in the new internal connections. This full recompilation may take longer than an engineer would wish to wait; depending upon the device, compilation can take anywhere from one hour to one-half day, or even as long as two days. The re-place and re-route may also affect the signal that is being investigated. For example, the bug being investigated might disappear, or could change. Further, other problems may be introduced into the design, or the maximum frequency of the design may be adversely affected.
For these reasons, it is not always desirable to execute a full recompile in order to view an internal signal for purposes of debugging. What is desired is the ability to view an internal signal in an electronic design without affecting the current placement and routing, without breaking timing constraints, and without having to recompile the entire design.